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6384DS–ATARM–13-Jan-10
AT91SAM9G20 Summary
7.2.3
Masters to Slaves Access
All the Masters can normally access all the Slaves. However, some paths do not make sense,
like as example allowing access from the Ethernet MAC to the Internal Peripherals. Thus, these
paths are forbidden or simply not wired, and shown “-” in Table 7-3.
7.3
Peripheral DMA Controller
Acting as one Matrix Master
Allows data transfers from/to peripheral to/from any memory space without any intervention
of the processor.
Next Pointer Support, forbids strong real-time constraints on buffer management.
Twenty-four channels
– Two for each USART
– Two for the Debug Unit
– Two for the Serial Synchronous Controller
– Two for each Serial Peripheral Interface
– One for Multimedia Card Interface
– One for Analog-to-Digital Converter
– Two for the Two-wire Interface
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-
lowing priorities (Low to High priorities):
– TWI Transmit Channel
– DBGU Transmit Channel
– USART5 Transmit Channel
– USART4 Transmit Channel
– USART3 Transmit Channel
– USART2 Transmit Channel
– USART1 Transmit Channel
– USART0 Transmit Channel
– SPI1 Transmit Channel
Table 7-3.
AT91SAM9G20 Masters to Slaves Access
Master
0 & 1
234
5
Slave
ARM926
Instruction &
Data
Peripheral
DMA
Controller
ISI
Controller
Ethernet
MAC
USB Host
Controller
0
Internal SRAM
16 Kbytes
XX
X
1
Internal SRAM
16 Kbytes
XX
X
2
Internal ROM
X
-
UHP User Interface
X
-
3
External Bus Interface
X
4
Internal Peripherals
X
-
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